Page last modified 01:56, 8 Mar 2014 by jsousa
IPFN > FUSION Collaborations > ITER > CODAC > FPSC > ATCA-IO-PROCESSOR
Table of contents
- 1. Summary
TOC
- 1. Summary
Other pages:
Summary
Endereço base deste projecto no servidor SVN do cdaq:
Endereço base do projecto da placa anterior:
Endereço base do projecto da placa de 250/400 MSPS:
Diagrama de blocos actual da FPGA
IRIG info:
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Files 6
| File | Size | Date | Attached by | |||
|---|---|---|---|---|---|---|
 | | FPGA HDL diagram (beta).pdf No description | 33.2 kB | 16:19, 14 Apr 2011 | jsousa | Actions |
| IRIG-B.pdf No description | 73.73 kB | 18:05, 4 Mar 2011 | jsousa | Actions | |
| IRIGB_timecode.pdf No description | 385.42 kB | 18:05, 4 Mar 2011 | jsousa | Actions | |
| TN-102_IRIG-B.pdf No description | 709.35 kB | 18:05, 4 Mar 2011 | jsousa | Actions | |
| TrueTime_IRIG200-95_spec.pdf No description | 292.63 kB | 18:05, 4 Mar 2011 | jsousa | Actions | |
| wp-irig-200-98.pdf No description | 368.74 kB | 18:05, 4 Mar 2011 | jsousa | Actions | |
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