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Page last modified 10:57, 29 Nov 2011 by toquim

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    Version as of 10:05, 12 Apr 2025

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    • Tracks width and differential pairs spacing in order to achieve a thinner PCB;
    • Galvanic isolation tracks spacing;
    • J2 Footprint;
    • J59 Footprint;
    • Keepout keying K1;
    • Test points silk screen;
    • References backannotation;
    • Solder mask U51, U55 and U58;
    • Terminations position;
    • Decoupling capacitors position;
    • FTM connector’s replacement;
    • Front panel adjustments;
    • RTM mechanical issues;
    • Rear panel adjustments;
    • Possibility of RTM with LEMO connectors;
    • Possibility of replacig the FPGA by other with more resources; 
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