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Page last modified 16:44, 16 Oct 2012 by toquim

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    Version as of 10:13, 12 Apr 2025

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    • Tracks width and differential pairs spacing in order to achieve a thinner PCB;
    • Galvanic isolation tracks spacing;
    • J2 Footprint;
    • J59 Footprint;
    • Keepout keying K1;
    • Test points silk screen;
    • References backannotation;
    • Solder mask U51, U55 and U58;
    • Terminations position;
    • Decoupling capacitors position;
    • FTM connector’s replacement;
    • RTM mechanical thickness; 
    • Increase space for the fan header;
    • Handle switch position;
    • Pin 1 position U20 and U21 (silk screen);
    • IPMC correction;
    • FPGA pinout;
    • FPGA I2C voltage translator - enable connected to an IPMC output or to the payload enable;
    • IPMC ICs on the board;
    • USB port.
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