Table of contents
No headers1st Progress Meeting report (13th December 2011):
- Board test plan in development (see respective section for details);
- Board production plan in development (see respective section for details);
- Board enginnering design in development (see respective section for details);
- Firmware validated for path one and two;
- PCI express generation 2 validated;
- RTM modifications in standby until all analog IO channels are tested;
- Board tests to be done listed into the To test section;
- Searching in progress for a new PCB design company to make changes in order to improve the ATCA-IO-PROCESSOR prototype PCB;
2nd Progress Meeting report (10th January 2012):
Hardware:
- Board test plan first draft ready;
- Board production plan first draft ready;
- Board enginnering design first draft ready;
- Hardware engineering files and hardware production files to be stored on ITER SVN, folder structure created.
Firmware:
- Improving the stability on the continuos aquisition data streaming ( DMA channel #2)
Software:
- Luca Boncagni finished his develloping and tunning the MARTe system to receive RT data
(report still to be finished) - Progressing on device driver devellopemt to handle DMA channel #2
Next month
Hardware:
- Board production (4 units) in progress;
- Hardware engineering files and hardware production files to be stored on ITER SVN, files upload in progress;
- RTM modifications in progress;
- Board tests to be done listed into the To test section;
- Searching in progress for a new PCB design company to make changes in order to improve the ATCA-IO-PROCESSOR prototype PCB.
Firmware:
- Integration of IPMC module with geographical address of ATCA boards on system
- Implementattion of fast data dat transfer ( DMA channel #3)
Software:
-Progressing on device driver devellopemt to handle DMA channel #2 and #3
-device Suport modules to EPICS