ATCA-PTSW-AMC4
Table of contents
The ATCA-AMC-CARRIER board is a cutaway quad-AMC carrier module compliant with the ATCA (PICMG 3.0) specification. Below are summarized its main charateristics.
PCIE-RTM
PCI Express switch
Switching is performed by a PLX PEX8696 (PCIe Gen 2)
PCI Express (PICMG 3.4) switching of:
- 13 fabric channels (×4 links), connecting up to 13 compliant modules within the shelf
- 4 AMC modules (×4 links)
- 1 RTM module (×8 link)
- Onboard FPGA (×4 link)
Crosspoint-switch for ATCA, AMC and RTM clock distribution
- Implemented on a Virtex-6 FPGA.
- The crosspoint-switch distributes clocking signals to all AMC/RTM cards within the board.
- Connection to compliant modules within the shelf is assured via the ATCA clock and synchronization interface.
- Each clock signal source may be independently located (any of the AMCs, the RTM or ATCA backplane).
Rear Transmission Module
- Compliant with PICMG 3.8 (ARTM)
- Connectivity:
- 1 PCI Express channel (×16 link)
- 1 full-duplex RapidIO channel (×4 link) to each AMC slot
- 1 full-duplex RapidIO channel (×4 link) to the FPGA (MGT transceivers)
- 8 LVDS pairs to each AMC slot
- 8 LVDS pairs to the FPGA (SelectIO)
- 1 GbE channel (connects to AMC1)
IPMC controller
- CoreIPM OPMA2368
- Hardware management of all AMCs and RTM (IPMB-L)
Block diagram of the board:
Connector Pinouts
Table 1. PCI Express over cable lanes mapping on the ARTM connector.
| Con | Pin | Signal | Con | Pin | Signal | Con | Pin | Signal | Con | Pin | Signal |
| Rp33 | F1 | Port_0_Tx- | Rp33 | F3 | Port_4_Tx- | Rp33 | F5 | Port_8_Tx- | Rp33 | F7 | Port_12_Tx- |
| Rp33 | E1 | Port_0_Tx+ | Rp33 | E3 | Port_4_Tx+ | Rp33 | E5 | Port_8_Tx+ | Rp33 | E7 | Port_12_Tx+ |
| Rp33 | H1 | Port_0_Rx- | Rp33 | H3 | Port_4_Rx- | Rp33 | H5 | Port_8_Rx- | Rp33 | H7 | Port_12_Rx- |
| Rp33 | G1 | Port_0_Rx+ | Rp33 | G3 | Port_4_Rx+ | Rp33 | G5 | Port_8_Rx+ | Rp33 | G7 | Port_12_Rx+ |
| Rp33 | B1 | Port_1_Tx- | Rp33 | B3 | Port_5_Tx- | Rp33 | B5 | Port_9_Tx- | Rp33 | B7 | Port_13_Tx- |
| Rp33 | A1 | Port_1_Tx+ | Rp33 | A3 | Port_5_Tx+ | Rp33 | A5 | Port_9_Tx+ | Rp33 | A7 | Port_13_Tx+ |
| Rp33 | D1 | Port_1_Rx- | Rp33 | D3 | Port_5_Rx- | Rp33 | D5 | Port_9_Rx- | Rp33 | D7 | Port_13_Rx- |
| Rp33 | C1 | Port_1_Rx+ | Rp33 | C3 | Port_5_Rx+ | Rp33 | C5 | Port_9_Rx+ | Rp33 | C7 | Port_13_Rx+ |
| Rp33 | F2 | Port_2_Tx- | Rp33 | F4 | Port_6_Tx- | Rp33 | F6 | Port_10_Tx- | Rp33 | F8 | Port_14_Tx- |
| Rp33 | E2 | Port_2_Tx+ | Rp33 | E4 | Port_6_Tx+ | Rp33 | E6 | Port_10_Tx+ | Rp33 | E8 | Port_14_Tx+ |
| Rp33 | H2 | Port_2_Rx- | Rp33 | H4 | Port_6_Rx- | Rp33 | H6 | Port_10_Rx- | Rp33 | H8 | Port_14_Rx- |
| Rp33 | G2 | Port_2_Rx+ | Rp33 | G4 | Port_6_Rx+ | Rp33 | G6 | Port_10_Rx+ | Rp33 | G8 | Port_14_Rx+ |
| Rp33 | B2 | Port_3_Tx- | Rp33 | B4 | Port_7_Tx- | Rp33 | B6 | Port_11_Tx- | Rp33 | B8 | Port_15_Tx- |
| Rp33 | A2 | Port_3_Tx+ | Rp33 | A4 | Port_7_Tx+ | Rp33 | A6 | Port_11_Tx+ | Rp33 | A8 | Port_15_Tx+ |
| Rp33 | D2 | Port_3_Rx- | Rp33 | D4 | Port_7_Rx- | Rp33 | D6 | Port_11_Rx- | Rp33 | D8 | Port_15_Rx- |
| Rp33 | C2 | Port_3_Rx+ | Rp33 | C4 | Port_7_Rx+ | Rp33 | C6 | Port_11_Rx+ | Rp33 | C8 | Port_15_Rx+ |
Table 2. Giga-bit Ethernet mapping on the ARTM connector.
| Con | Pin | Signal | Interface[1] |
| Rp33 | B9 | GbE_Port_0_Tx- | AMC #1 Site |
| Rp33 | A9 | GbE_Port_0_Tx+ | |
| Rp33 | D9 | GbE_Port_0_Rx- | |
| Rp33 | C9 | GbE_Port_0_Rx+ | |
| Rp32 | F7 | GbE_Port_1_Tx- | FPGA Ethernet Port #0 |
| Rp32 | E7 | GbE_Port_1_Tx+ | |
| Rp32 | H7 | GbE_Port_1_Rx- | |
| Rp32 | G7 | GbE_Port_1_Rx+ |