Logged in: Logged in as: Log in
Search:
Page last modified 14:55, 9 Jan 2012 by jsousa

Test Plan

    Table of contents
    No headers

    Version as of 06:01, 19 Apr 2025

    to this version.

    Return to Version archive.

    View current version

     

    • PCIe cable connection (Gen1, Gen2);
    • AXIe signals;
    • MLVDS timing signals;
    • Fabric PCIe connections (Gen1, Gen2);
    • Digital IO timing signals (RTM);
    • IPMC;
    • SFP (RTM);
    • Firmware: IEEE-1588-2008, IRIG generator, timing signals switch;
    Powered by MindTouch Core